1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly to an electrostatic protection circuit with high reliability.
2. Description of the Related Art
In a first example of a conventional electrostatic protection circuit shown in FIG. 1, a common wiring pattern 110 is provided on a semiconductor chip. Each of all terminals such as a power supply (Vdd) terminal 101, a ground (GND) terminal 102, and input/output terminals 103 and the common wiring pattern are connected by a parallel protection element composed of a parasitic bipolar element and a diode element. In the electrostatic protection circuit having such a structure, a completely equivalent discharge path can be established in any combination of any terminals and also any positive or negative application voltage mode. Therefore, the electrostatic protection circuit having high reliability can be easily provided.
The operation of the electrostatic protection circuit will be described with reference to FIG. 1. Referring to FIG. 1, all terminals including the power supply (Vdd) terminal 101 and the ground (GND) terminal 102 are connected to the common wiring pattern 110 by the protection element, i.e., a parallel circuit composed of a bipolar element and a diode. When a positive electrostatic pulse is applied to the input terminal 103 with respect to the GND terminal as a reference point, a discharge path is the path of the input terminal 103.fwdarw.the bipolar element Q103 of the input terminal.fwdarw.the common wiring pattern 110.fwdarw.the diode D102 of the GND terminal.fwdarw.GND terminal 102. Current flows through this discharge path to protect an internal circuit 120. Also, in a case where a negative electrostatic pulse is applied to the input terminal 103 with respect to the GND terminal 102 as the reference point, current flows through the discharge path of the GND terminal 102.fwdarw.the bipolar element Q102 of the GND terminal.fwdarw.the common wiring pattern 110.fwdarw.the diode D103 of the input terminal.fwdarw.the input terminal 103, to protect the internal circuit.
FIG. 2 shows the current (I)--voltage (V) characteristics between the ground terminal 102 and one of the terminals other than the ground terminal 102, e.g., the input terminal 103, when the impedance of the internal circuit 120 is infinite in the first conventional example shown in FIG. 1, that is, when only the electrostatic protection circuit and the common wiring pattern are connected to each of these terminals. In this case, when an over-voltage is applied between the ground terminal 102 and the other terminal such as the input terminal 103 and the over-voltage reaches Vtp (Vtm in case of the negative over-voltage), a trigger current starts to flow through the protection element. When the trigger current higher than a threshold value flows, the bipolar element operates to clamp the applied voltage to a predetermined voltage of Vsbp (Vsbm). In this case, the current flows through the bipolar element and the diode, even when the over-voltage is a positive polarity or a negative polarity. Therefore, if a parasitic resistance can be ignored, the clamped voltage can be expressed as EQU Vsbp=.vertline.Vsbm.vertline.=Vc+Vbi,
where Vc is the clamped voltage by the bipolar element and Vbi is the built-in voltage of the diode. For example, when a bipolar element is the parasitic bipolar transistor manufactured in a MOSLSI process in accordance with the 0.6-.mu. rule, Vc is about 7 V and Vbi is about 0.9 V. As seen from these values, the clamped voltage Vsbp and .vertline.Vsbm.vertline. are about 8 V. In this way, when the internal circuit 120 is not connected to the terminals 102 and 103, the electrostatic protection circuit operates completely symmetrically and operates ideally.
However, actually, there is a case that the internal circuit 120 has the impedance characteristic shown in FIG. 3, resulting in degradation of protection capability. The reason of the degradation of the protection capability will be described below in detail.
FIG. 3 shows the I-V characteristic of the internal circuit 110 with a voltage being applied between the power supply terminal 101 and the ground terminal 102. When a positive voltage is applied to the terminal 101 or 103 with respect to the ground terminal 102, current does not flow, because the impedance of the internal circuit 120 is high. In accordance with, the current first starts to flow through the protection element as mentioned above. When the current reaches the trigger current, the bipolar element starts to operate to clamp the applied voltage. In this case, because most of the current flows through the protection element and the common wiring pattern 110, the internal circuit 120 can be protected.
On the other hand, when a negative voltage is applied to the internal circuit 120 with respect to the ground terminal 102, there is a case that the impedance of the internal circuit 120 is low, as shown in FIG. 3. In this case, because an absolute value .vertline.Vsbm.vertline. of the clamped voltage is larger than the applied negative voltage even if the protection element enters the operation state, a lot of current flows through the internal circuit 120. When this current centers on a small area of the internal circuit 120, an element in the small area is sometimes damaged or destroyed. Further, because the impedance of the internal circuit 120 is low, there is a case that the current does not flow sufficiently through the protection element so that the bipolar element does not operate.
As a consequence, in the conventional electrostatic protection circuit shown in FIG. 1, there is the following problem. That is, a sufficient protection performance can not sometimes achieved, depending on the structure of the internal circuit 120, when the negative over-voltage is applied to the other terminal with respect to the ground terminal 102.
Next, an example of the internal circuit 120 will be described with reference to FIG. 1. Referring to FIG. 1, an inverter Inv1 is composed of a P-type MOS transistor TP1 and an N-type MOS transistor TN1, and an inverter Inv2 is composed of a P-type MOS transistor TP2 and an N-type MOS transistor TN2 in the same way. The input of the inverter Inv1 is selectively connected to one of an internal signal .phi. and the ground (GND) potential in accordance with selection of a wiring pattern master slice switch SW.
For example, when the wiring pattern master slice switch SW is fixedly switched to the ground (GND) potential, the above-mentioned problem occurs. That is, when a positive voltage with respect to the Vdd terminal 101 is applied to the GND terminal 102, the N-type MOS transistor TN1 is set to the conductive state. Further, a PN junction between a P.sup.+ -type impurity diffusion layer of the source/drain region of the P-type MOS transistor and an N well, i.e., a diode DS is set to a forward direction bias state, and a current flows to the Vdd terminal 101 via the N well. In this case, when the threshold voltage of the N-type MOS transistor TN1 is, for example, 0.7 V, the voltage with which the current abruptly increases in FIG. 3, i.e., a threshold voltage is about 1.6 V, because the built-in voltage of the diode DS is 0.9 V.
The threshold voltage of the electrostatic protection circuit is generally determined based on a breakdown voltage of the N.sup.+ -type impurity diffusion layer, and is about 14 V. Therefore, when a positive surge voltage is applied to the GND terminal 102, large current flows through the inverter Inv1 so that degradation of the junction is caused or a gate insulating film is damaged.
In the above-mentioned example, whether or not it results in the destruction of the internal circuit 120 is greatly dependent upon the circuit structure of the internal circuit 120. Also, it depends on the dimension and layout of each element in the discharge path, e.g., the element shape, the wiring pattern impedance and so on, and is determined based on the magnitude of the discharge current and the concentration degree of the current.
FIG. 4 is a circuit diagram illustrating a second conventional example of the electrostatic protection circuit which is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 2-119169). In the second conventional example, each of the terminals PIN1, PIN2 and PINn is connected to the common wiring pattern 110 by a parallel circuit composed of a thyristor and a diode. In this case, when a positive electrostatic pulse is applied to, for example, the pin 2 with respect to the pin 1 as a reference point, a discharge path is formed of the pin 1 PIN1.fwdarw.the thyristor of the pin 1 PIN.fwdarw.the common wiring pattern 110.fwdarw.the diode of the pin 2 PIN2.fwdarw.the pin 2 PIN2. When a negative electrostatic pulse is applied to the pin 2 with respect to the pin 1 as the reference point, a discharge current flows through the discharge path of the pin 2 PIN2.fwdarw.the thyristor of the pin 2 PIN2.fwdarw.the common wiring pattern 110.fwdarw.the diode of the pin 1 PIN1.fwdarw.the pin 1 PIN1, to protect the internal circuits Z.
FIG. 5 shows the I-V characteristic between the arbitrarily selected two pins when the internal impedance of the electrostatic protection circuit shown in FIG. 4 is infinite. The clamped voltage Vsbp can be represented as Vsbp=.vertline.Vsbm.vertline.=Vc+Vbi, like the case to be shown in FIG. 1. In this case, because the thyristor is used for a clamp element, the voltage Vc is about 1.5 V and this value is low, compared to the bipolar element in the first conventional example of FIG. 1. In accordance with, the clamped voltage Vsbp is Vsbp=.vertline.Vsbm.vertline.=1.5 V+0.9 V=2.4 V.
A problem of this electrostatic protection circuit is as follows. That is, if the thyristor as the protection element starts to such operate due to a cause as, e.g., power supply noise when the semiconductor circuit is normally used, a lot of current flows from the power supply terminal through the ground terminal, because the clamped voltage Vsbp is low. This current continues to flow until the power supply voltage is decreased to a voltage lower than the clamped voltage Vsbp of about 2.4 V (this is so-called latch-up phenomenon). In the worst case, there is the possibility to cause destruction of any element.